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SY10EP52VKI

-3.3V~-5V 4GHz D-Type Flip Flop 10EP52 47mA 10EP Series 8-TSSOP, 8-MSOP (0.118, 3.00mm Width)


  • Manufacturer: Microchip Technology
  • Origchip NO: 536-SY10EP52VKI
  • Package: 8-TSSOP, 8-MSOP (0.118, 3.00mm Width)
  • Datasheet: PDF
  • Stock: 817
  • Description: -3.3V~-5V 4GHz D-Type Flip Flop 10EP52 47mA 10EP Series 8-TSSOP, 8-MSOP (0.118, 3.00mm Width)(Kg)

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Details

Tags

Parameters
Mounting Type Surface Mount
Package / Case 8-TSSOP, 8-MSOP (0.118, 3.00mm Width)
Supplier Device Package 8-MSOP
Operating Temperature -40°C~85°C TA
Packaging Tube
Published 2005
Series 10EP
Part Status Discontinued
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Type D-Type
Voltage - Supply -3.3V~-5V
Base Part Number 10EP52
Function Standard
Output Type Differential
Number of Elements 1
Clock Frequency 4GHz
Current - Quiescent (Iq) 47mA
Number of Bits per Element 1
Trigger Type Positive, Negative
RoHS Status Non-RoHS Compliant

SY10EP52VKI Overview


The flip flop is packaged in 8-TSSOP, 8-MSOP (0.118, 3.00mm Width). It is contained within the Tubepackage. This output is configured with Differential. It is configured with a trigger that uses a value of Positive, Negative. Surface Mountis occupied by this electronic component. The JK flip flop operates at a voltage of -3.3V~-5V. It is operating at a temperature of -40°C~85°C TA. It belongs to the type D-Typeof flip flops. In this case, it is a type of FPGA belonging to the 10EP series. It should not exceed 4GHzin its output frequency. D latch consists of 1 elements. As a result, it consumes 47mA of quiescent current without being affected by external factors. D latch belongs to the 10EP52 family.

SY10EP52VKI Features


Tube package
10EP series

SY10EP52VKI Applications


There are a lot of Microchip Technology SY10EP52VKI Flip Flops applications.

  • Shift Registers
  • Computers
  • Data transfer
  • Automotive
  • Reduced system switching noise
  • Consumer
  • Functionally equivalent to the MC10/100EL29
  • Cold spare funcion
  • Clock pulse
  • High Performance Logic for test systems