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  • T1042NSN7MQB

T1042NSN7MQB

0.8mm PowerPC e5500 32-bit Microprocessor QorIQ T1 Series 1V 780-FBGA, FCBGA


  • Manufacturer: NXP USA Inc.
  • Origchip NO: 568-T1042NSN7MQB
  • Package: 780-FBGA, FCBGA
  • Datasheet: PDF
  • Stock: 630
  • Description: 0.8mm PowerPC e5500 32-bit Microprocessor QorIQ T1 Series 1V 780-FBGA, FCBGA (Kg)

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Details

Tags

Parameters
Factory Lead Time 18 Weeks
Package / Case 780-FBGA, FCBGA
Surface Mount YES
Operating Temperature 0°C~105°C TA
Packaging Bulk
Published 2014
Series QorIQ T1
Part Status Active
Moisture Sensitivity Level (MSL) 3 (168 Hours)
Number of Terminations 780
ECCN Code 3A991.A.1
HTS Code 8542.31.00.01
Technology CMOS
Terminal Position BOTTOM
Terminal Form BALL
Peak Reflow Temperature (Cel) 250
Supply Voltage 1V
Terminal Pitch 0.8mm
JESD-30 Code S-PBGA-B780
Supply Voltage-Max (Vsup) 1.03V
Supply Voltage-Min (Vsup) 0.97V
Speed 1.4GHz
uPs/uCs/Peripheral ICs Type MICROPROCESSOR, RISC
Core Processor PowerPC e5500
Clock Frequency 133.3MHz
Bit Size 32
Address Bus Width 16
Boundary Scan YES
Low Power Mode YES
External Data Bus Width 64
Format FIXED POINT
Integrated Cache YES
Ethernet 1Gbps (5)
Number of Cores/Bus Width 4 Core 64-Bit
Graphics Acceleration No
RAM Controllers DDR3L/4
USB USB 2.0 + PHY (2)
Additional Interfaces I2C, MMC/SD, PCIe, SPI, UART
SATA SATA 3Gbps (2)
Height Seated (Max) 2.07mm
Length 23mm
RoHS Status ROHS3 Compliant

T1042NSN7MQB Description


The T1042NSN7MQB advanced multicore processor combines with high-performance data path acceleration and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and military/aerospace applications.

This T1042NSN7MQB can be used for combined control, data path, and application layer processing in routers, switches, gateways, and general-purpose embedded computing systems. Its high level of integration offers significant performance benefits compared to multiple discrete devices, while also simplifying board design.



T1042NSN7MQB Features


e5500 cores built on Power Architecture? technology

256 KB shared L3 CoreNet platform cache (CPC)

Hierarchical interconnect fabric

One 32-/64-bit DDR3L/DDR4 SDRAM memory controllers

Data Path Acceleration Architecture (DPAA)

Eight SerDes lanes for high-speed peripheral interfaces



T1042NSN7MQB Applications


Combined control

Data path

Routers

Switches

Gateways

General-purpose embedded computing systems