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XCR3064XL-7CPG56C

0.5mm PMIC 56 Pin 3.3V

Manufacturer: Xilinx
Origchip NO: 903-XCR3064XL-7CPG56C
Package: -
Datasheet: -
Stock: 237
Description: 0.5mm PMIC 56 Pin 3.3V (Kg)

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Details

Tags

Parameters
Frequency (Max)	119MHz
Programmable Logic Type	EE PLD
Number of Gates	1500
Number of Logic Blocks (LABs)	4
Speed Grade	7
Output Function	MACROCELL
Number of Macro Cells	64
JTAG BST	YES
In-System Programmable	YES
Height Seated (Max)	1.35mm
Length	6mm
Width	6mm
RoHS Status	RoHS Compliant
Mount	Surface Mount
Number of Pins	56
JESD-609 Code	e1
Pbfree Code	yes
Moisture Sensitivity Level (MSL)	3
Number of Terminations	56
ECCN Code	EAR99
Max Operating Temperature	70°C
Min Operating Temperature	0°C
Additional Feature	YES
Subcategory	Programmable Logic Devices
Technology	CMOS
Terminal Position	BOTTOM
Terminal Form	BALL
Peak Reflow Temperature (Cel)	260
Supply Voltage	3.3V
Terminal Pitch	0.5mm
Time@Peak Reflow Temperature-Max (s)	30
Pin Count	56
Qualification Status	Not Qualified
Operating Supply Voltage	3.3V
Supply Voltage-Max (Vsup)	3.6V
Temperature Grade	COMMERCIAL
Number of I/O	48
Memory Type	EEPROM
Propagation Delay	7.5 ns

XCR3064XL-7CPG56C Overview

In the mobile phone network, there are 64macro cells, which are cells with high-power antennas and towers.There are 48 I/Os programmed in it.It is programmed that device terminations will be 56 .The terminal position of this electrical part is BOTTOM, which serves as an important access point for passengers or freight.Power is provided by a supply voltage of 3.3V volts.This part is in the family [0].It is equipped with 56 pin count.It is also characterized by YES.1500gates are used to construct digital circuits.If high efficiency is desired, the supply voltage should be kept at [0].For storing data, it is recommended to use [0].It is mounted by Surface Mount.The 56pins are designed into the board.3.6Vis the maximum supply voltage (Vsup).It is recommended that the operating temperature be greater than 0°C.The operating temperature should be lower than 70°C.In its simplest form, it consists of 4 logic blocks (LABs).It is recommended that the maximum frequency is less than 0.This kind of FPGA is composed of EE PLD.

XCR3064XL-7CPG56C Features

48 I/Os
56 pin count
56 pins
4 logic blocks (LABs)

XCR3064XL-7CPG56C Applications

There are a lot of Xilinx XCR3064XL-7CPG56C CPLDs applications.

I/O PORTS (MCU MODULE)
INTERRUPT SYSTEM
Storage Cards and Storage Racks
State machine control
Custom state machines
Dedicated input registers
Interface bridging
State machine design
Wide Vin Industrial low power SMPS
Digital designs